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general description the max13030e?ax13035e 6-channel, bidirectional level translators provide the level shifting necessary for 100mbps data transfer in multivoltage systems. the max13030e?ax13035e are ideally suited for memo- ry-card level translation, as well as generic level trans- lation in systems with six channels. externally applied voltages, v cc and v l , set the logic levels on either side of the device. logic signals present on the v l side of the device appear as a higher voltage logic signal on the v cc side of the device and vice versa. the max13035e features a clk_ret output that returns the same clock signal applied to the clk_v l input. the max13030e?ax13035e operate at full speed with external drivers that source as little as 4ma output current. each i/o channel is pulled up to v cc or v l by an internal 30? current source, allowing the max13030e?ax13035e to be driven by either push- pull or open-drain drivers. the max13030e?ax13034e feature an enable (en) input that places the device into a low-power shutdown mode when driven low. the max13030e?ax13035e features an automatic shutdown mode that disables the part when v cc is less than v l . the state of i/o v cc_ and i/o v l_ during shutdown is chosen by selecting the appropriate part version (see ordering information/ selector guide ). the max13030e?ax13035e accept v cc voltages from +2.2v to +3.6v and v l voltages from +1.62v to +3.2v, making them ideal for data transfer between low-voltage asic/plds and higher voltage systems. the max13030e?ax13035e are available in 16-bump ucsp (2mm x 2mm) and 16-pin tqfn (4mm x 4mm) packages, and operate over the extended -40? to +85? temperature range. applications sd card level translation minisd card level translation mmc level translation transflash level translation memory stick card level translation features compatible with 4ma input drivers or larger 100mbps guaranteed data rate six bidirectional channels clock return output (max13035e) enable input (max13030e?ax13034e) ?5kv esd protection on i/o v cc lines +1.62v v l +3.2v and +2.2v v cc +3.6v supply voltage range lead-free, 16-bump ucsp (2mm x 2mm) and 16-pin tqfn (4mm x 4mm) packages max13030e?ax13035e 6-channel high-speed logic-level translators ________________________________________________________________ maxim integrated products 1 19-0626; rev 0; 1/07 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available ordering information/selector guide gnd gnd gnd +1.8v system controller +3.3v sd card v l v cc clk_ret clk_v cc clock_in +3.3v +1.8v clk_v l 0.1 f 1 f 0.1 f max13035e dat3 dat2 dat1 dat0 cmd clock i/o v l_ i/o v l_ i/o v l_ i/o v l_ i/o v l_ i/o v cc_ i/o v cc_ i/o v cc_ i/o v cc_ i/o v cc_ dat3 dat2 dat1 dat0 cmd clock typical operating circuits part pin-package i/o v l _ state during shutdown i/o v cc _ state during shutdown pkg code max13030e ebe+ 16 ucsp high impedance high impedance b16-1 max13030eete+ 16 tqfn-ep** high impedance high impedance t1644-4 functional diagram and pin configurations appear at end of data sheet. typical operating circuits continued at end of data sheet. note: all devices are specified over the -40? to +85? operating temperature range. + denotes a lead-free package. ** ep = exposed paddle. ordering information/selector guide continued at end of data sheet.
max13030e?ax13035e 6-channel high-speed logic-level translators 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (all voltages referenced to gnd.) v cc , v l .....................................................................-0.3v to +4v i/o v cc_ , clk_v cc ....................................-0.3v to (v cc + 0.3v) i/o v l_ , clk_v l , clk_ret ..........................-0.3v to (v l + 0.3v) en.............................................................................-0.3v to +4v short-circuit duration i/o v l_ , i/o v cc_ , clk_v cc , clk_v l , clk_ret to gnd.......................continuous continuous power dissipation (t a = +70?) 16-bump ucsp (derate 8.2mw/?) ..............................660mw 16-pin tqfn (derate 25.0mw/?)...............................2000mw operating temperature range ...........................-40? to +85? storage temperature range .............................-65? to +150? junction temperature ......................................................+150? bump temperature (soldering)........................................+235? lead temperature (soldering, 10s) .................................+300? electrical characteristics (v cc = +2.2v to +3.6v, v l = +1.62v to +3.2v, en = v l , t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, v l = +1.8v and t a = +25?.) (notes 1, 2) parameter symbol conditions min typ max units power supplies v l supply range v l (note 2) 1.62 3.20 v v cc supply range v cc 2.2 3.6 v supply current from v cc i qvcc i/o v cc _ = v cc , i/o v l _ = v l 16 25 ? supply current from v l i qvl i/o v cc _ = v cc , i/o v l _ = v l 610a t a = +25?, en = gnd or v l > v cc + 0.7v, max13030e?ax13034e 24 v cc shutdown supply current i shdn-vcc t a = +25?, v l > v cc + 0.7v, max13035e, 24 ? t a = +25?, en = gnd or v l > v cc + 0.7v, max13030e?ax13034e 0.1 4 v l shutdown supply current i shdn-vl t a = +25?, v l > v cc + 0.7v, max13035e 0.1 4 ? i/o v cc_ , i/o v l_ , clk_v cc tri-state leakage current i leak t a = +25?, en = gnd or v l > v cc + 0.7v 0.1 2 a en input leakage current i leak _ en t a = +25?, max13030e?ax13034e 1 a v l - v cc shutdown threshold high v th_h v cc rising -0.2 0.05v l 0.7 v v l - v cc shutdown threshold low v th_l v cc falling -0.2 0.1v l 0.7 v i/o v cc_ pulldown resistance during shutdown r vcc _ pd _ sd en = gnd, max13032e/max13034e 10 16.5 23 k i/o v cc_ pullup resistance during shutdown r vcc _ pu _ sd en = gnd, max13031e 10 16.5 23 k i/o v l_ pulldown resistance during shutdown r vl _ pd _ sd en = gnd, max13033e/max13034e 10 16.5 23 k
max13030e?ax13035e 6-channel high-speed logic-level translators _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units i/o v l_ , clk_v l , clk_ret pullup resistance during shutdown r vl _ pu _ sd (v l > v cc + 0.7v), max13035e 45 75 105 k i/o v l_ , clk_v l , clk_ret pullup current r vl_pu en = v cc or v l , i/o v l_ = gnd 20 ? i/o v cc_ , clk_v cc pullup current r vcc_pu en = v cc or v l , i/o v cc_ = gnd 20 ? i/o v l to i/o v cc dc resistance r iovl_iovcc (note 3) 3 k esd protection (note 3) human body model, c vcc = 1.0? ?5 iec 61000-4-2 air-gap discharge, c vcc = 1.0? ?2 i/o v cc_ , clk_v cc iec 61000-4-2 contact discharge, c vcc = 1.0? ? kv logic-level thresholds i/o v l_, clk_v l input-voltage high threshold v ihl (note 4) v l - 0.2 v i/o v l_, clk_v l input-voltage low threshold v ill (note 4) 0.15 v i/o v cc_ , clk_v cc input- voltage high threshold v ihc (note 4) v cc - 0.4 v i/o v cc_ , clk_v cc input- voltage low threshold v ilc (note 4) 0.2 v en input-voltage high threshold v ih max13030e?ax13034e v l - 0.4 v en input-voltage low v il max13030e?ax13034e 0.4 v i/o v l_ , clk_v l , clk_ret output-voltage high v ohl i/o v l_ , clk_v l , clk_ret source current = 20?, i/o v cc _ v cc - 0.4v 2/3 v l v i/o v l_ , clk_v l , clk_ret output-voltage low v oll i/o v l_ , clk_v l , clk_ret sink current = 20?, i/o v cc _ 0.2v 1/3 v l v i/o v cc _, clk_v cc output- voltage high v ohc i/o v cc _, clk_v cc source current = 20?, i/o v l _ v l - 0.2v 2/3 v cc v electrical characteristics (continued) (v cc = +2.2v to +3.6v, v l = +1.62v to +3.2v, en = v l , t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, v l = 1.8v and t a = +25?.) (notes 1, 2)
max13030e?ax13035e 6-channel high-speed logic-level translators 4 _______________________________________________________________________________________ parameter symbol conditions min typ max units i/o v cc_ , clk_v cc output- voltage low v olc i/o v cc_ , clk_v cc sink current = 20?, i/o v l _ 0.15v 1/3 v cc v rise/fall time accelerator stage (note 3) on falling edge 3 accelerator pulse duration on rising edge 3 ns v l = 1.62v 11 v l -output-accelerator source impedance v l = 3.2v 6 v cc = 2.2v 9 v cc -output-accelerator source impedance v cc = 3.6v 8 v l = 1.62v 9 v l -output-accelerator sink impedance v l = 3.2v 8 v cc = 2.2v 10 v cc -output-accelerator sink impedance v cc = 3.6v 9 electrical characteristics (continued) (v cc = +2.2v to +3.6v, v l = +1.62v to +3.2v, en = v l , t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, v l = 1.8v and t a = +25?.) (notes 1, 2) parameter symbol conditions min typ max units i/o v cc _, clk_v cc rise time t rvcc r s = 150 , c i/ovcc = 10pf, c clk_vcc = 10pf, push-pull drivers (figure 1) 2.5 ns i/o v cc _, clk_v cc fall time t fvcc r s = 150 , c i /ov c c = 10p f, c c lk _v c c = 10p f ( figures 1, 2) 2.5 ns i/o v l _, clk_v l rise time t rvl r s = 150 , c i /ov l = 15p f, c c lk _v l = 15p f, push-pull drivers (figure 3) 2.5 ns i/o v l _, clk_v l fall time t fvl r s = 150 , c i /ov l = 15p f, c c lk _v l = 15p f ( figures 3, 4) 2.5 ns propagation delay (driving i/o v l _, clk_v l ) t pvl-vcc r s = 150 , c i/ovcc = 10pf, c clk_vcc = 10pf, push-pull drivers (figure 1) 6.5 ns propagation delay (driving i/o v cc _, clk_v cc ) t pvcc-vl r s = 150 , c i /ov l = 15p f, c c lk _v l = 15p f, push-pull drivers (figure 3) 6.5 ns channel-to-channel skew t skew r s = 150 , c i /ov c c = 10p f, c i /ov l = 15p f 0.8 ns propagation delay from i/o v l_ to i/o v cc_ after en t en-vcc r load = 1m , c i/ovcc = 10pf (figure 5) (max13030e?ax13034e) 5s timing characteristics (v cc = +2.2v to +3.6v, v l = +1.62v to +3.2v, c i/ovl 15pf, c i/ovcc 15pf, r source = 150 , en = v l , i/o v l_ to i/o v cc_ rise/fall time = 3ns, t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, v l = 1.8v and t a = +25?.) (note 1)
max13030e?ax13035e 6-channel high-speed logic-level translators _______________________________________________________________________________________ 5 parameter symbol conditions min typ max units propagation delay from i/o v cc_ to i/o v l_ after en t en-vl r load = 1m , c i/ovl = 15pf (figure 5) (max13030e?ax13034e) 5s maximum data rate push-pull operation, r source = 150 _ , c i/ovcc_ = 10pf, c i/ovl_ = 15pf, c clk_vcc = 10pf, c clk_vl = 15pf 100 mbps timing characteristics (continued) (v cc = +2.2v to +3.6v, v l = +1.62v to +3.2v, c i/ovl 15pf, c i/ovcc 15pf, r source = 150 , en = v l , i/o v l_ to i/o v cc_ rise/fall time = 3ns, t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, v l = 1.8v and t a = +25?.) (note 1) note 1: all units are 100% production tested at t a = +25?. limits over the operating temperature range are guaranteed by design and not production tested. note 2: v l must be less than or equal to v cc - 0.2v during normal operation. however, v l can be greater than v cc during startup and shutdown conditions and the part will not latch-up or be damaged. note 3: guaranteed by design. note 4: input thresholds are referenced to the boost circuit.
max13030e?ax13035e 6-channel high-speed logic-level translators 6 _______________________________________________________________________________________ typical operating characteristics (v cc = 3.3v, v l = 1.8v, c l = 15pf, r source = 150 , data rate = 100mbps, push-pull driver, t a = +25?, unless otherwise noted.) 750 780 770 760 800 790 840 830 820 810 850 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v l supply current vs. v cc supply voltage (driving i/o v l_ , v l = 1.8v) max13030e toc01 v cc supply voltage (v) v l supply current ( a) driving one i/o v l 0 2 1 4 3 6 5 7 9 8 10 1.6 2.0 2.2 1.8 2.4 2.6 2.8 3.0 3.2 v l supply current vs. v l supply voltage (driving i/o v cc_ , v cc = 3.6v) max13030e toc02 v l supply voltage (v) v l supply current (ma) driving one i/o v cc 5.0 10.0 7.5 15.0 12.5 22.5 20.0 17.5 25.0 2.2 2.6 2.4 2.8 3.0 3.2 3.4 3.6 v cc supply current vs. v cc supply voltage (driving i/o v l_ , v l = 1.8v) max13030e toc03 v cc supply voltage (v) v cc supply current (ma) driving one i/o v l 15.0 16.0 15.5 17.0 16.5 18.0 17.5 18.5 19.5 19.0 20.0 1.6 2.0 2.2 1.8 2.4 2.6 2.8 3.0 3.2 v cc supply current vs. v l supply voltage (driving i/o v cc_ , v cc = 3.6v) max13030e toc04 v l supply voltage (v) v cc supply current (ma) driving one i/o v cc 0 4 2 10 8 6 16 14 12 18 -40 10 -15 35 60 85 supply current vs. temperature (driving i/o v cc_ ) max13030e toc05 temperature ( c) supply current (ma) driving one i/o v cc i cc i l 0 6 4 2 8 10 12 14 16 18 20 -40 10 -15 35 60 85 supply current vs. temperature (driving i/o v l_ ) max13030e toc06 temperature ( c) supply current (ma) i cc i l driving one i/o v l 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 10 20 15 25 30 35 40 v l supply current vs. capacitive load on i/o v l_ (driving i/o v cc_ ) max13030e toc07 capacitive load (pf) v l supply current (ma) driving one i/o v cc 16.0 16.5 17.0 17.5 18.0 18.5 19.0 19.5 20.0 10 20 15 25 30 35 40 v cc supply current vs. capacitive load on i/o v cc_ (driving i/o v l_ ) max13030e toc08 capacitive load (pf) v cc supply current (ma) driving one i/o v l 500 800 700 600 900 1000 1100 1200 1300 1400 1500 10 20 15 25 30 35 40 rise/fall time vs. capacitive load on i/o v cc_ (driving i/o v l_ ) max13030e toc09 capacitive load (pf) rise/fall time (ps) t rvcc t fvcc
max13030e?ax13035e 6-channel high-speed logic-level translators _______________________________________________________________________________________ 7 typical operating characteristics (continued) (v cc = 3.3v, v l = 1.8v, c l = 15pf, r source = 150 , data rate = 100mbps, push-pull driver, t a = +25?, unless otherwise noted.) 500 1250 1000 750 1500 1750 2000 2250 2500 2750 3000 10 20 15 25 30 35 40 rise/fall time vs. capacitive load on i/o v l_ (driving i/o v cc_ ) max13030e toc10 capacitive load (pf) rise/fall time (ps) t rvl t fvl 2.0 3.0 2.5 4.0 3.5 4.5 5.0 10 20 25 15 30 35 40 propagation delay vs. capacitive load on i/o v cc_ (driving i/o v l_ ) max13030e toc11 capacitive load (pf) propagation delay (ns) t plh t phl 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 10 20 15 25 30 35 40 propagation delay vs. capacitive load on i/o v l_ (driving i/o v cc_ ) max13030e toc12 capacitive load (pf) propagation delay (ns) t phl t plh 10ns/div typical i/o v l_ driving (frequency = 26mhz, c iovcc = 40pf) i/o v l_ 1v/div i/o v cc_ 2v/div max13030e toc13 10ns/div typical i/o v cc_ driving (frequency = 26mhz, c iovl = 15pf) i/o v cc_ 2v/div i/o v l_ 1v/div max13030e toc14 10ns/div typical clk_ v l driving (frequency = 26mhz, c clk_vcc = 40pf) clk_ v l 1v/div clk_ret 1v/div max13030e toc15 clk_ v cc 2v/div
max13030e?ax13035e 6-channel high-speed logic-level translators 8 _______________________________________________________________________________________ pin description pin max13030e?ax13034e max13035e ucsp tqfn ucsp tqfn name function a1 4 a1 4 i/o v l 3 input/output 3. referenced to v l . a2 6 a2 6 i/o v cc 3 input/output 3. referenced to v cc . a3 7 a3 7 i/o v cc 4 input/output 4. referenced to v cc . a4 9 a4 9 i/o v l 4 input/output 4. referenced to v l . b1 3 b1 3 i/o v l 2 input/output 2. referenced to v l . b2 5 b2 5 i/o v cc 2 input/output 2. referenced to v cc . b3 8 b3 8 i/o v cc 5 input/output 5. referenced to v cc . b4 10 b4 10 i/o v l 5 input/output 5. referenced to v l . c1 2 c1 2 v l logic-supply voltage, +1.62v to +3.2v. bypass v l to gnd with a 0.1? capacitor placed as close as possible to the device. c2 16 c2 16 v cc power-supply voltage, +2.2v to +3.6v. bypass v cc to gnd with a 0.1? ceramic capacitor. for full esd protection, connect a 1? ceramic capacitor from v cc to gnd as close as possible to the v cc input. c3 13 c3 13 gnd ground c4 11 en enable input. drive en to gnd for shutdown mode, or drive en to v l or v cc for normal operation. d1 1 d1 1 i/o v l 1 input/output 1. referenced to v l . d2 15 d2 15 i/o v cc 1 input/output 1. referenced to v cc . d3 14 i/o v cc 6 input/output 6. referenced to v cc . d4 12 i/o v l 6 input/output 6. referenced to v l . c4 11 clk_ret clock return output. clk_ret is the returned signal of a clock applied to clk_v l . clk_ret is referenced to v l . d3 14 clk_v cc translator channel for a clock applied to v cc d4 12 clk_v l translator channel for a clock applied to v l ep ep ep exposed paddle. connect exposed paddle to gnd.
max13030e?ax13035e 6-channel high-speed logic-level translators _______________________________________________________________________________________ 9 test circuits/timing diagrams max13030e max13035e t fvcc t rvcc i/o v l_ (clk_v l *) i/o v cc_ (clk_v cc *) 150 v l v l v cc 10% 10% 90% 90% 50% 50% 50% 50% v cc c iovcc t plh t phl t pvl-vcc = t plh or t phl v cc en** v l i/o v cc i/o v l *max13035e only (c clk_vcc *) **max13030e?ax13034e only figure 1. push-pull driving i/o v l_ test circuit and timing max13030e max13035e t fvcc t rvcc v l v l v cc 10% 10% 90% 90% 50% 50% 50% 50% v cc c iovcc i/o v cc v gate v l v cc en** v gate i/o v l_ (clk_v l *) i/o v cc_ (clk_v cc *) *max13035e only **max13030e?ax13034e only (c clk_vcc *) t plh t phl t pvl-vcc = t phl figure 2. open-drain driving i/o vl_ test circuit and timing
max13030e?ax13035e 6-channel high-speed logic-level translators 10 ______________________________________________________________________________________ test circuits/timing diagrams (continued) max13030e max13035e t fvl t rvl v l v l v cc 10% 10% 90% 90% 50% 50% 50% 50% v cc c iovl i/o v cc v l v cc en** 150 i/o v l i/o v l_ (clk_v l *) (c clk_vl *) i/o v cc_ (clk_v cc *) *max13035e only **max13030e?ax13034e only t plh t phl t pvcc-vl = t plh or t phl figure 3. push-pull driving i/o v cc_ test circuit and timing max13030e max13035e v l v l v cc 10% 10% 90% 90% 50% 50% 50% 50% v cc c iovl i/o v l v l v cc en** t fvl t rvl v gate i/o v l_ (clk_v l *) (c clk_vl *) (c clk_vl *) i/o v cc_ (clk_v cc *) *max13035e only **max13030e?ax13034e only t plh t phl t pvcc-vl = t phl figure 4. open-drain driving i/o v cc_ test circuit and timing
max13030e?ax13035e 6-channel high-speed logic-level translators ______________________________________________________________________________________ 11 test circuits/timing diagrams (continued) max13030e max13034e source i/o v cc_ c iovcc r load en v l 0 v l v cc 0 0 i/o v l_ i/o v cc_ v cc / 2 en v l i/o v l_ source c iovcc i/o v cc_ en i/o v l_ r load v cc t' en-vcc en v l 0 v l v cc 0 0 i/o v l_ t en-vcc is whichever is larger between t' en-vcc and t" en-vcc . i/o v cc_ v cc / 2 t" en-vcc v l v cc v l v cc v l v cc v l v cc max13030e max13034e source v cc en v l 0 v cc v l 0 0 i/o v cc_ i/o v l_ v l / 2 en i/o v l_ i/o v cc_ source en t' en-vl en v l 0 v cc v l 0 0 i/o v cc_ t en-vcc is whichever is larger between t' en-vcc and t" en-vcc . i/o v l_ v l / 2 t" en-vl c iovl r load r load c iovl i/o v l_ i/o v cc_ v l max13030e max13034e max13030e max13034e figure 5. enable test circuit and timing
max13030e?ax13035e detailed description the max13030e?ax13035e 6-channel, bidirectional level translators provide the level shifting necessary for 100mbps data transfer in multivoltage systems. the max13030e?ax13035e are ideally suited for memory card level translation, as well as generic level translation in systems with six channels. externally applied volt- ages, v cc and v l , set the logic levels on either side of the device. logic signals present on the v l side of the device appear as a higher voltage logic signal on the v cc side of the device, and vice versa. the max13035e features a clk_ret output that returns the same clock signal applied to the clk_v l input. the max13030e?ax13035e operate at full speed with external drivers that source as little as 4ma output current. each i/o channel is pulled up to v cc or v l by an internal 30? current source, allowing the max13030e?ax13035e to be driven by either push- pull or open-drain drivers. the max13030e?ax13034e feature an enable (en) input that places the device into a low-power shutdown mode when driven low. the max13030e?ax13035e features an automatic shutdown mode that disables the part when v cc is less than v l . the state of i/o v cc_ and i/o v l_ during shutdown is chosen by selecting the appropriate part version (see ordering information/ selector guide ). the max13030e?ax13035e accept v cc voltages from +2.2v to +3.6v and v l voltages from +1.62v to +3.2v. level translation for proper operation, ensure that +2.2v v cc +3.6v, and +1.62v v l v cc - 0.2v. when power is supplied to v l while v cc is either missing or less than v l , the max13030e?ax13035e automatically enters a low- power mode. in addition, the max13030e max13034e enters a low-power mode if en = 0v. this allows v cc to be disconnected and still have a known state on i/o v l_ . the maximum data rate depends heavily on the load capacitance (see the typical operating characteristics rise/fall times ), output impedance of the driver, and the operating voltage range. input driver requirements the max13030e?ax13035e architecture is based on an nmos pass gate and output accelerator stages (see figure 6). output accelerator stages are always in tri- state mode except when there is a transition on any of the translators on the input side, either i/o v l_ , clk_v l , i/o v cc_ , or clk_v cc . a short pulse is then generated during which the output accelerator stages become active and charge/discharge the capacitances at the i/os. due to its architecture, both input stages become active during the one-shot pulse. this can lead to some current feeding into the external source that is driving the translator. however, this behavior helps to speed up the transition on the driven side. the max13030e?ax13035e have internal current sources capable of sourcing 30? to pullup the i/o lines. these internal pullup current sources allow the inputs to be driven with open-drain drivers, as well as push-pull drivers. it is not recommended to use exter- nal pullup resistors on the i/o lines. the architecture of the max13030e?ax13035e permit either side to be driven with a minimum of 4ma drivers or larger. output load requirements the max13030e?ax13035e i/o are designed to drive cmos inputs. do not load the i/o lines with a resistive load less than 25k and do not place an rc circuit at the input of these devices to slow down the edges. if a slower rise/fall time is required, refer to the max3000e/ max3001e logic-level translator datasheet. for i 2 c level translation, refer to the max3372e?ax3379e/ max3390e?ax3393e datasheet. shutdown mode the max13030e?ax13034e feature an enable (en) input that places the device into a low-power shutdown mode when driven low. the max13030e?ax13035e features an automatic shutdown mode that disables the part when v cc is missing or less than v l . 6-channel high-speed logic-level translators 12 ______________________________________________________________________________________ 30 a v l enable enable enable v cc 30 a boost circuit i/o v l_ v l v cc boost circuit v cc v l i/o v cc_ notes: 1) the max13030e?ax13034e are enabled when v l < v cc - 0.2v and en = v l . 2) the max13035e is enabled when v l < v cc - 0.2v . figure 6. simplified functional diagram for one i/o line
clock return (clk_ret) the max13035e features a clk_ret output that returns the clock signal applied to clk_v l . clk_v l and clk_v cc are identical to the other i/o channels, the only difference being that clk_v cc is internally tied to the v cc side of clk_ret (see the functional diagram ). application information layout recommendations use standard high-speed layout practices when laying out a board with the max13030e?ax13035e. for example, to minimize line coupling, place all other signal lines not connected to the max13030e?ax13035e at least 1x the substrate height of the pcb away from the input and output lines of the max13030e?ax13035e. power-supply decoupling to reduce ripple and the chance of introducing data errors, bypass v l and v cc to ground with 0.1? ceram- ic capacitors. place all capacitors as close as possible to the power-supply inputs. for full esd protection, bypass v cc with a 1? ceramic capacitor located as close as possible to the v cc input. unidirectional vs. bidirectional level translator the max13030e?ax13035e bidirectional level trans- lators can operate as a unidirectional device to trans- late signals without inversion. these devices provide the smallest solution (ucsp package) for unidirectional level translation without inversion. use with external pullup/pulldown resistors due to the architecture of the max13030e max13035e, it is not recommended to use external pullup or pulldown resistors on the bus. in certain appli- cations, the use of external pullup or pulldown resistors is desired to have a known bus state when there is no active driver on the bus. for example, this may happen when interfacing to a memory card slot with no memory card inserted. the max13030e?ax13035e include internal pullup current sources that set the bus state when the device is enabled. in shutdown mode, the state of i/o v cc_ and i/o v l_ is dependent on the selected part version (see ordering information/ selector guide for further information). open-drain signaling the max13030e?ax13035e are designed to pass open-drain as well as cmos push-pull signals. when used with open-drain signaling, the rise time is domi- nated by the interaction of the internal pullup current source and the parasitic load capacitance. the max13030e?ax13035e include internal rise time accelerators to speed up transitions, eliminating any need for external pullup resistors. sd card detection sd, minisd, mmc and similar types of cards provide detection of a card through a pullup resistor on one of the dat lines, or by use of a mechanical switch. this pullup resistor is internal to the memory card itself. the max13030e?ax13035e only support detection of a memory card through a mechanical switch, and it is recommended that the internal resistor for card detection be switched off by the command interface. for example, when using sd cards, the command set_clr_card_detect (acmd42) disables this resistor. ucsp applications information for the latest application details on ucsp construction, dimensions, tape carrier information, pcb techniques, bump-pad layout, and recommended reflow tempera- ture profiles, as well as the latest information on reliabil- ity testing results, go to maxim? web site at www.maxim-ic.com/ucsp to find the application note: ucsp ?a wafer-level chip-scale package. chip information process: bicmos max13030e?ax13035e 6-channel high-speed logic-level translators ______________________________________________________________________________________ 13
max13030e?ax13035e 6-channel high-speed logic-level translators 14 ______________________________________________________________________________________ max13030e max13034e v l v cc max13035e v l v cc i/o v l 1 i/o v l 2 i/o v l 3 i/o v l 4 i/o v l 5 clk_ v l clk_ret i/o v l 1 i/o v l 2 i/o v l 3 i/o v l 4 i/o v l 5 i/o v l 6 i/o v l 1 i/o v cc 1 i/o v cc 2 i/o v cc 3 i/o v cc 4 i/o v cc 5 i/o v cc 6 gnd en gnd i/o v cc 1 i/o v cc 2 i/o v cc 3 i/o v cc 4 i/o v cc 5 clk_ v cc functional diagram
max13030e?ax13035e 6-channel high-speed logic-level translators ______________________________________________________________________________________ 15 16 tqfn (4mm x 4mm) gnd 16 1234 12 11 10 9 15 14 13 5 6 7 8 v cc i/o v cc 1 i/o v cc 6 i/o v l 6 en i/o v l 5 i/o v l 4 v l i/o v l 2 i/o v l 3 i/o v cc 2 i/o v cc 3 i/o v cc 4 i/o v cc 5 i/o v l 1 max13030e max13034e top view *ep + *connect exposed paddle to ground 16 ucsp (2mm x 2mm) a b c 12 3 4 i/o v cc 3 i/o v l 4 i/o v l 3 i/o v cc 4 i/o v cc 2 i/o v l 5 i/o v l 2 i/o v cc 5 max13030e?ax13034e v cc en v l gnd top view (bumps on bottom) d i/o v cc 1 i/o v l 6 i/o v l 1 i/o v cc 6 + pin configurations 16 tqfn (4mm x 4mm) gnd 16 1234 12 11 10 9 15 14 13 5 6 7 8 v cc i/o v cc 1 clk_v cc clk_v l clk_ret i/o v l 5 i/o v l 4 v l i/o v l 2 i/o v l 3 i/o v cc 2 i/o v cc 3 i/o v cc 4 i/o v cc 5 i/o v l 1 max13035e top view *ep + *connect exposed paddle to ground 16 ucsp (2mm x 2mm) a b c 12 3 4 i/o v cc 3 i/o v l 4 i/o v l 3 i/o v cc 4 i/o v cc 2 i/o v l 5 i/o v l 2 i/o v cc 5 max13035e v cc clk_ret v l gnd top view (bumps on bottom) d i/o v cc 1 clk_v l i/o v l 1 clk_v cc +
max13030e?ax13035e 6-channel high-speed logic-level translators 16 ______________________________________________________________________________________ gnd gnd gnd +1.8v system controller +3.3v system v l v cc i/o v l_ i/o v cc_ data data +3.3v +1.8v en en 0.1 f 1 f 0.1 f max13030e max13034e 6 6 typical operating circuits (continued) part pin-package i/o v l _ state during shutdown i/o v cc _ state during shutdown pkg code max13031e ebe+* 16 ucsp high impedance 16.5k to v cc b16-1 max13031eete+* 16 tqfn-ep** high impedance 16.5k to v cc t1644-4 max13032e ebe+ 16 ucsp high impedance 16.5k to gnd b16-1 max13032eete+ 16 tqfn-ep** high impedance 16.5k to gnd t1644-4 max13033e ebe+* 16 ucsp 16.5k to gnd high impedance b16-1 max13033eete+* 16 tqfn-ep** 16.5k to gnd high impedance t1644-4 max13034e ebe+* 16 ucsp 16.5k to gnd 16.5k to gnd b16-1 max13034eete+* 16 tqfn-ep** 16.5k to gnd 16.5k to gnd t1644-4 max13035e ebe+ 16 ucsp 75k to v l high impedance b16-1 max13035eete+ 16 tqfn-ep** 75k to v l high impedance t1644-4 ordering information/selector guide (continued) note: all devices are specified over the -40? to +85? operating temperature range. + denotes a lead-free package. ** ep = exposed paddle.
max13030e?ax13035e 6-channel high-speed logic-level translators ______________________________________________________________________________________ 17 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 16l,ucsp.eps h 1 1 21-0101 package outline, 4x4 ucsp
max13030e?ax13035e 6-channel high-speed logic-level translators maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. boblet 24l qfn thin.eps package outline, 21-0139 2 1 e 12, 16, 20, 24, 28l thin qfn, 4x4x0.8mm package outline, 21-0139 2 2 e 12, 16, 20, 24, 28l thin qfn, 4x4x0.8mm package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
e nglish ? ???? ? ??? ? ??? what's ne w p roducts solutions de sign ap p note s sup p ort buy comp any me mbe rs m axim > p roduc ts > i nterfac e and i nterc onnec t max13030e, max13031e*, max13032e, max13033e*, max13034e*, max13035e 6-c hannel high-speed logic-level translators high-speed (100mbps), 6-channel translators compatible with 4ma drivers * future product for automatic e-mail on new parts in this product line, subscribe to ee-mail quickview technical documents ordering info more information all ordering information notes: other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 1. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 2. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming c onventions . 3. * some packages have variations, listed on the drawing. "pkgc ode/variation" tells which variation the product uses. 4. devices: 1-12 of 12 m ax13030e fre e sam ple buy pack age : type pins footprint drawing code/var * te m p rohs/le ad-fre e ? m ate rials analys is max13030eete+t thin qfn;16 pin;17 mm dwg: 21-0139g (pdf) use pkgcode/variation: t1644+4 * -40c to +85c rohs/lead-free: lead free materials analysis max13030eete+ thin qfn;16 pin;17 mm dwg: 21-0139g (pdf) use pkgcode/variation: t1644+4 * -40c to +85c rohs/lead-free: lead free materials analysis max13030eebe+ uc sp;16 pin;4 mm dwg: 21-0101h (pdf) use pkgcode/variation: b16+1 * -40c to +85c rohs/lead-free: lead free materials analysis max13030eebe+t uc sp;16 pin;4 mm dwg: 21-0101h (pdf) use pkgcode/variation: b16+1 * -40c to +85c rohs/lead-free: lead free materials analysis m ax13032e fre e sam ple buy pack age : type pins footprint drawing code/var * te m p rohs/le ad-fre e ? m ate rials analys is max13032eete+t thin qfn;16 pin;17 mm dwg: 21-0139g (pdf) use pkgcode/variation: t1644+4 * -40c to +85c rohs/lead-free: lead free materials analysis max13032eete+ thin qfn;16 pin;17 mm dwg: 21-0139g (pdf) use pkgcode/variation: t1644+4 * -40c to +85c rohs/lead-free: lead free materials analysis max13032eebe+ uc sp;16 pin;4 mm dwg: 21-0101h (pdf) use pkgcode/variation: b16+1 * -40c to +85c rohs/lead-free: lead free materials analysis max13032eebe+t uc sp;16 pin;4 mm dwg: 21-0101h (pdf) use pkgcode/variation: b16+1 * -40c to +85c rohs/lead-free: lead free materials analysis m ax13035e fre e sam ple buy pack age : type pins footprint drawing code/var * te m p rohs/le ad-fre e ? m ate rials analys is
max13035eete+t thin qfn;16 pin;17 mm dwg: 21-0139g (pdf) use pkgcode/variation: t1644+4 * -40c to +85c rohs/lead-free: lead free materials analysis max13035eete+ thin qfn;16 pin;17 mm dwg: 21-0139g (pdf) use pkgcode/variation: t1644+4 * -40c to +85c rohs/lead-free: lead free materials analysis max13035eebe+t uc sp;16 pin;4 mm dwg: 21-0101h (pdf) use pkgcode/variation: b16+1 * -40c to +85c rohs/lead-free: lead free materials analysis max13035eebe+ uc sp;16 pin;4 mm dwg: 21-0101h (pdf) use pkgcode/variation: b16+1 * -40c to +85c rohs/lead-free: lead free materials analysis didn't find what you need? next day product selection assistance from applications engineers parametric search applications help quickview technical documents ordering info more information des c ription key features a pplic ations /u s es key spec ific ations diagram data sheet a pplic ation n otes des ign guides e ngineering journals reliability reports software/m odels e valuation kits p ric e and a vailability samples buy o nline p ac kage i nformation lead-free i nformation related p roduc ts n otes and c omments e valuation kits doc ument ref.: 1 9 -0 6 2 6 ; rev 0 ; 2 0 0 7 -0 2 -1 2 t his page las t modified: 2 0 0 7 -0 2 -1 2 c ontac t us: send us an email c opyright 2 0 0 7 by m axim i ntegrated p roduc ts , dallas semic onduc tor ? legal n otic es ? p rivac y p olic y

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